1. Field of the Invention
The present invention relates to a program control method and an apparatus to achieve and perform stall processing in a computer system which executes instructions using pipeline processing.
2. Description of the Related Art
A computer system, such as a digital signal processor (hereinafter referring to as a DSP), which executes instructions using pipeline processing, includes a dedicated pointer register (hereinafter referring to as PR) to perform data memory addressing. In such a computer system, the competition of the resource such as register interference is occasionally caused between the instructions.
For instance, when a computer system uses four step pipeline, there are four processing stages, an instruction fetch stage (IF), an instruction decode 1 stage (D1), an instruction decode 2 stage (D2), and execution stage (EX). Data transmission from GR to PR is performed in the EX stage. Moreover, the data memory addressing for PR is performed in the D1 stage. Therefore, when an instruction with an access to the data memory (For instance, move operation from the data memory to GR:MOV GR, M(PR)) is performed just after an instruction for move operation (MOV PR,GR) from GR to PR, a memory addressing is performed by using the previous value of PR. This phenomenon causes a problem of the register interference.
In order to prevent the resource competition such as register interference and the like, an instruction stall method is adopted, which instruction stall method is inserting the no operation instruction (hereinafter referring to as NOP) between the instructions by which the resource competition is caused. An unexamined Japanese patent application Tokkai-Hei 1-119829 is known technology that solves and performs the problem of the resource competition. Technology disclosed in the unexamined Japanese patent application Tokkai-Hei 1-119829 prevents the register interference in computer system processing by stall control for defining a NOP field for specifying the number of NOP in an instruction code, detecting the specified number of NOP to be inserted by referencing the NOP field in an instruction code decoding stage, and inserting NOP of the predetermined number following the output of execution internal code of the instruction code.
According to this technology, the NOP field is assigned in the instruction code, the number of NOP which is inserted after execution of an instruction concerned is specified in the NOP field in the instruction causing the resource competition such as register interference etc. By the information specified in the NOP field, the stall is executed between a preceding instruction and the following instruction causing the resource competition such as register interference, and the resource competition can be prevented. When a computer system uses four step pipeline processing, memory addressing with new value of the PR renewed in the preceding instruction (instruction 1) processing can be performed by inserting 2 NOP between the preceding instruction 1 (MOV PR, GR) and the following instruction 2 (MOV GR, M(PR)).
However, in the above-mentioned unexamined Japanese patent application Tokkai-Hei 1-119829 concrete hardware configuration to achieve the stall control by referencing NOP field of the instruction code and inserting predetermined number of NOP is not disclosed at all.
According to the technology disclosed in the unexamined Japanese patent application Tokkai-Hei 1-119829, when a preceding instruction and a following instruction cause resource competition such as register interference, the NOP field is assigned in the preceding instruction, and the number of NOP is set and necessary number of NOP cycle is inserted after executing the preceding instruction.
However, the instruction codes where the NOP field is assigned becomes large when the kind of the preceding instruction causing the resource competition in the processing program occurs often. It is not preferable to overly increment the instruction code where the NOP field is assigned because it results in increasing the instruction code data amount.
Moreover, it is impossible to use this method according to the conventional method of assigning the NOP field in the preceding instruction code when there is not enough available field space for the NOP field.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a program control apparatus for performing stall control by inserting NOP of the predetermined number into the process referring to the NOP field in an instruction code.
It is an another object of the present invention to provide a method of a program control and an apparatus for suppressing an increase of the instruction code data amount according to the NOP insertion for the stall control when resource competing.
It is an another object of the present invention to provide a method of the program control and an apparatus for improving the available field space compared with a conventional method when the available field space for the NOP field in the instruction code is small.
In order to achieve the objects, a program control method for performing stall processing for a computer system wherein an instruction is operated by using a pipeline processing in accordance with the invention includes the following steps: A step for assigning NOP field which indicates the number of NOP (no operation processing) in an instruction code and a step for decoding the instruction code and inserting N pieces of NOP when the number of NOP specified in the NOP field after executing the instruction corresponding to the instruction code.
According to the above processing, when a preceding instruction and the following instruction cause resource competition in the processing program, the program control method of this invention can insert NOP after the preceding instruction is executed and the following instruction is executed after NOP. The stall control can be achieved.
It is a preferable concerning setting the number of NOP to the NOP field that an assembler or a compiler automatically performs setting the number of NOP to the instruction code where there is a possibility of competition of the resource. As for the second and third method of the program control of the following description, automatically setting of the number of NOP is preferable.
Next, when a preceding instruction and a following instruction cause a resource competition in a processing program, and the kind of the following instruction is less than the kind of the preceding instruction, it is preferable that the NOP field is assigned in the following instruction code.
According to the above processing, when the kind of the following instruction is less than the kind of the preceding instruction among instructions causing resource competition, the number of instructions where the NOP field is assigned as a whole can be reduced by assigning the NOP field in the following instruction code rather than in the preceding instruction code.
In order to achieve the objects, a second program control method of this invention for performing stall processing for a computer system wherein an instruction is operated by using a pipeline processing, when a preceding instruction and a following instruction cause resource competition in a processing program, includes the following steps: A step for assigning the NOP field in both the preceding instruction code and the following instruction code, a step for inserting set number of NOP specified in the preceding instruction after executing the instruction corresponding to the preceding instruction code and a step for inserting set number of NOP specified in the following instruction before executing the instruction corresponding to the following instruction code.
According to the above processing, when there is not enough available field space in the instruction code of either a preceding instruction or a following instruction or both, the available field space will be improved by assigning the NOP field both in the preceding instruction code and in the following instruction code.
A program control apparatus of the present invention for processing an instruction by using a pipeline processing which instruction includes NOP field for specifying the number of NOP to be inserted includes the following parts: An instruction code storage part for storing first instruction codes, an address generation part for generating an address for outputting the first instruction code from the instruction code storage part and a stall control part for inputting the first instruction code, for controlling an output of a stop signal to stop a pipeline processing stage to the address generation part temporarily based on the result of the detection whether inputted first instruction code includes NOP field or not, and for controlling an output signal of either the first instruction code or a NOP code as a second instruction code.
According to the above configuration, the apparatus of the present invention can temporarily stop the pipeline processing stage and stall control according to the detection result whether there is NOP field in the input instruction code or not.
It is preferable that the program control apparatus wherein the stall control part further includes following parts: A first instruction register latches the first instruction code which is read out from the instruction code storage part and a switch part is for inputting the first instruction code outputted from the first instruction register and NOP code and for selecting and outputting either the first instruction code or NOP code as an second instruction code based on a switching signal. Also a temporary pipeline stop part for inputting the second instruction code which is outputted from the switch part, for detecting whether the inputted second instruction code is an instruction which includes NOP field or not, for controlling output of the stop signal to the address generation part and the first instruction register based on the detecting result, and for controlling the output of the switching signal to the switch part is included.
According to the above configuration, NOP can be executed by a second instruction code is outputted and a pipeline processing stage is stopped temporarily when the first input instruction code is an instruction code which has the NOP field.
In this case, the second instruction code is outputted from stall control part, the second instruction code is executed before NOP.
Next, it is preferable that the stall control part further includes the following parts: A first instruction register latches the first instruction code which read out from the instruction code storage part and a second instruction register latches the first instruction code which is read out from the first instruction register. Also a switch part for inputting the first instruction code outputted from the second instruction register and NOP code and for selecting and outputting either the first instruction code or NOP code as an second instruction code based on a switching signal and a temporary pipeline stop part for inputting the first instruction code which is outputted from the first instruction register, for detecting whether the inputted first instruction code is an instruction which includes NOP field or not, for controlling output of the stop signal to the address generation part and both the first instruction register and second instruction register based on the detecting result, and for controlling the output of the switching signal to the switch part are included.
According to the above configuration, when the first instruction code is an instruction code which has the NOP field, Pipeline processing is stopped temporarily and the NOP code is outputted as the second code according to the switch signal.
In this case, the latched first instruction code is outputted as the second instruction code, the instruction code is output from stall control part after NOP is executed, afterwards the instruction code is executed.
Next, it is preferable that the stall control part further includes the following parts: A first instruction register latches the first instruction code which read out from the instruction code storage part and a first switch part for inputting the first instruction code outputted from the first instruction register and NOP code and for selecting and outputting either the first instruction code or NOP code based on a first switching signal. Also a second instruction register latches the output signal of the first switch part and a second switch part for inputting the output signal outputted from the second instruction register and NOP code and for selecting and outputting either the output signal of the second instruction register or NOP code as a second instruction code based on a second switching signal are included. A temporary pipeline stop part for inputting the output signal which is outputted from the switch part, for detecting whether the inputted signal is an instruction which includes NOP field or not, for controlling output of the stop signal to the address generation part and the first instruction register and another stop signal to the second instruction register based on the detecting result, and for controlling the output of the switching signal to the first switch part and the second switching part is included.
According to the above configuration, the NOP field space assigned in about one instruction can be reduced by assigning the NOP field in both parties of the first instruction code and the second instruction code, executing NOP of the predetermined number after the first instruction code is executed, and executing and performing NOP of the predetermined number before the second instruction code is executed.
When the field space by which the NOP field is assigned in the instruction code is small, the program control apparatus of the present invention is especially effective.
The number of NOP which the bit row in the NOP field shows can not be limited to a binary value, and it is possible to decide the combination of the bit row showing a specific numerical value.
Next, it is preferable that the temporary pipeline stop part includes the following parts: A NOP number counter is for counting the number of the NOP specified in the NOP field assigned in the instruction code and a detection part for detecting the inputted instruction code is an instruction which includes NOP field or not. The detection part outputs the stop signal while specified cycles of pipeline processing stage corresponding to the NOP number which is outputted from the NOP number counter when detection part detects the inputted instruction is an instruction which includes the NOP field.
According to the above configuration, the program control apparatus of the present invention can perform the detection for an inputted instruction whether the specific instruction where the NOP field is assigned or not and the detection for the number of NOP which is set in the NOP field.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.